1. Field of the Invention
This invention relates to multi-memory apparatus, which includes two or more identical memory units with access to a common system bus (a standard bus), and methods that provide a secure memory performance in the event that various kinds of errors or fault conditions occur, whether employing essentially synchronous or parallel operation, without interruption. The invention thus provides a highly reliable multi-memory apparatus.
2. Description of the Related Art
FIG. 27 shows a conventional example of a multi-memory apparatus and its system configuration. As the figure illustrates the conventional multi-memory apparatus includes a pair of identical memory arrays 601 and 602, a pair of identical error detectors 608 and 609 and some functional elements such as a control circuit 611, an error corrector 610 and an output selector 613.
The operation of the conventional apparatus is now described with reference to the figure. When a read address is specified on a read address line 600, the address is stored in address selectors 603. 604, which are used to access the memory arrays 601 and 602 and thereby read memory data in parallel out of the specified addressed location into read registers 606 and 607, respectively. The read data from the memory arrays 601 and 602, in the absence of an error detected in the error detectors 608 and 609, are available for output. The error detectors provide an Input to a control circuit 611, which connects to an output selector 613. If there is no error, the output selector 618 selects either of them as output data.
When an error is detected in either of the error detectors, 608 or 609, the control circuit 611 receives the result of error detection. When an error is detected in the error detector 608, in other words a read error in the memory array 601, for example, the control circuit 611 informs the output selector 613 of the error in the memory circuit 601. The output selector 613 consequently selects the read data of the memory array 602 for output onto an output line 661.
In the meantime the error is corrected in the error corrector 610. The corrected data is written back into the memory array 601 in parallel with the output operation, using the address stored in write address register 605 and the content of the write flag register 612.
A similar operation occurs when an error is detected in the error detector 609, and a correction is made by corrector 610 and provided to memory array 602.
FIG. 28 shows another example of a conventional multi-memory apparatus illustrating a parallel operation with backup units. In the figure a master memory unit 712 and a backup memory unit 713 are identical and operate in parallel. In this system, data for output onto a data bus, which is not illustrated in the figure, generally is selected from the master memory unit. However, if there is an error detected in the master memory unit 712, the backup unit 713 will be selected. To secure parallel operation between the two memory units, they are controlled by a wired-OR technique employing OR gates 722 in the master memory unit and 732 in the backup memory unit. In other words, a bus-response operation has to be delayed until the both units gain a synchronous condition completing the whole course of the current response operation. A mode-change operation from/to master to/from backup between the memory units in the event of an error need not be described here, as it is well known.
The conventional art, therefore, leaves some challenges from an architectural point of view. As mentioned hereinbefore, the conventional multi-memory apparatus requires many additional functional elements, such as at least control circuits, for selecting correct data from between the memory units and output selectors. In other words, the conventional art requires more than a system configuration consisted of just two or more identical memory units to acquire synchronous backup operation in the system.
Besides, the conventional art provides no measures of securing synchronous as well as parallel operation among the memory units in the system when a new memory unit is replaced with a damaged master memory unit in the event of an error or failure detected in the master memory unit.